XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 202

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The Transmit Serial Clock (TxSerClk_n), Transmit Single-frame Synchronization Signal (TxSync_n) and Transmit
Multi-frame Synchronization Signal (TxMSync_n) can be either inputs or outputs depend on the timing source of
the Transmit section of the framer.
With the OSCCLK Driven Divided Clock or the Recovered Receive Line Clock being the timing source of the
transmit section, the Transmit Serial Clock (TxSerClk_n), Transmit Single-frame Synchronization Signal
(TxSync_n) and Transmit Multi-frame Synchronization Signal (TxMSync_n) are all outputs.
With the timing source of the transmit section being the Transmit Serial Input Clock, the Transmit Serial Clock
(TxSerClk_n), Transmit Single-frame Synchronization Signal (TxSync_n) and Transmit Multi-frame
Synchronization Signal (TxMSync_n) are all inputs.
The following table illustrates the input and output nature of these signals for different Transmit timing sources.
The Transmit Time-slot Indication Bits (TxTSb[4:0]_n) are multiplexed I/O pins. The functionality of these pins is
governed by the value of Transmit Fractional T1 Input Enable bit of the Transmit Interface Control Register
(TICR).
The following table illustrates the configurations of the Transmit Fractional DS1 Input Enable bit.
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0xn0H, 0x20H)
When configured to operate in normal condition (that is, when the Transmit Fractional T1 Input Enable bit is equal
to zero), these bits reflect the five-bit binary value of the Time Slot number (0 - 23) being accepted and processed
by the Transmit Payload Data Input Interface block of the framer. TxTSb[4] represents the MSB of the binary
value and TxTSb[0] represents the LSB.
N
Terminal Equipment Driven TxSerClk
UMBER
B
Recovered Receive Line Clock
OSCCLK Driven Divided Clock
4
IT
T
RANSMIT
Fractional DS1
Input Enable
B
Transmit
IT
T
IMING
N
AME
S
OURCE
T
ABLE
B
IT
R/W
T
36: S
YPE
IGNALS FOR DIFFERENT
0 - The Transmit Time-slot Indication bits (TxTSb[4:0] are outputting five-bit
binary values of Time-slot number (0-23) being accepted and processed by the
Transmit Payload Data Input Interface block of the framer.
The Transmit Time-slot Indicator Clock signal (TxTSClk_n) is a 192KHz clock
that pulses HIGH for one DS1 bit period whenever the Transmit Payload Data
Input Interface block is accepting the LSB of each of the twenty-four time slots.
1 - The TxTSb[0]_n bit becomes the Transmit Fractional T1 Input signal
(TxFrTD_n) which carries Fractional DS1 payload data into the framer.
The TxTSb[1]_n bit becomes the Transmit Signaling Data Input signal (TxSig_n)
which is used to insert robbed-bit signaling data into the outbound DS1 frame.
The TxTSb[2]_n bit serially outputs all five-bit binary values of the Time Slot
number (0-23) being accepted and processed by the Transmit Payload Data
Input Interface block of the framer.
The TxTSb[3]_n bit becomes the Transmit Overhead Synchronization Pulse
(TxOHSync_n) which is used to output an Overhead Synchronization Pulse that
indicates the first bit of each DS1multi-frame.
The TxTSClk_n will output gaped fractional DS1 clock that can be used by Ter-
minal Equipment to clock out Fractional DS1 payload data at rising edge of the
clock. Or,The TxTSClk_n pin will be a clock enable signal to Transmit Fractional
DS1 Input signal (TxFrTD_n) when the un-gaped Transmit Serail Input Clock
(TxSerClk_n) is used to clock in Fractional DS1 Payload Data into the framer.
T
X
S
Output
Output
ER
Input
C
LK
_
182
N
T
RANSMIT TIMING SOURCES
B
IT
T
D
X
Output
Output
ESCRIPTION
S
Input
YNC
_
N
T
X
MS
Output
Output
Input
YNC
REV. 1.0.1
_
N