XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 319

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
•
The Receive Back-plane Interface is pumping out data through RxSer_0 or RxSer_4 pins at 16.384Mbit/s. The
Receive High-speed Back-plane Interface multiplexes payload and signaling data of every four channels into
one data stream. Payload and signaling data of Channel 0-3 are multiplexed onto the Receive Serial Data pin
of Channel 0. Payload and signaling data of Channel 4-7 are multiplexed onto the Receive Serial Data pin of
Channel 4.
Free-running clocks of 16.384MHz are supplied to the Receive Serial Clock pin of Channel 0 and Channel 4 of
the framer. The Receive High-speed Back-plane Interface of the farmer provides data at rising edge of this
Receive Serial Clock. The local Terminal Equipment then latches incoming serial data at falling edge of the
clock.
The Receive High-speed Back-plane Interface maps four 2.048Mbit/s E1 data streams into this 16.384Mbit/s
data stream as described below:
FIRST OCTET OF 16.384MBIT/S DATA STREAM
THIRD OCTET OF 16.384MBIT/S DATA STREAM
FIFTH OCTET OF 16.384MBIT/S DATA STREAM
SEVENTH OCTET OF 16.384MBIT/S DATA STREAM
X
1. Payload data of four channels are repeated and grouped together in a byte-interleaved way. The first pay-
Y
Receive Time Slot indicator bits (RxTSb[4:0]_n)
: The Xth payload bit of Channel Y
load bit of Timeslot 0 of Channel 0 is sent first, followed by the second payload bit of Timeslot 0 of Channel
0 and so on. After all the bits of Timeslot 0 of Channel 0 is sent repeatedly, the Receive High-speed Back-
plane Interface will start sending the payload bits of Timeslot 0 of Channel 1 and 2. The payload bits of
Timeslot 0 of Channel 3 are sent the last.
After the payload bits of Timeslot 0 of all four channels are sent, it comes the payload bits of Timeslot 1 of
Channel 0 and so on. The table below demonstrates how payload bits of four channels are mapped into
the 16.384Mbit/s data stream.
B
B
B
B
1
1
1
1
IT
IT
IT
IT
0
1
2
3
0
0
0
0
B
B
B
B
1
1
1
1
IT
IT
IT
IT
0
1
2
3
1
1
1
1
B
B
B
B
2
2
2
2
IT
IT
IT
IT
0
1
2
3
2
2
2
2
B
B
B
B
2
2
2
2
IT
IT
IT
IT
0
1
2
3
3
3
3
3
299
B
B
B
B
3
3
3
3
IT
IT
IT
IT
0
1
2
3
4
4
4
4
B
B
B
B
3
3
3
3
IT
IT
IT
IT
0
1
2
3
5
5
5
5
OCTAL T1/E1/J1 FRAMER
B
B
B
B
4
4
4
4
IT
IT
IT
IT
0
1
2
3
6
6
6
6
XRT84L38
B
B
B
B
4
4
4
4
IT
IT
IT
IT
0
1
2
3
7
7
7
7