XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 53

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The Microprocessor Interface section supports communication between the local microprocessor (µP) and the
Framer. The Microprocessor Interface supports the following features:
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The Microprocessor Interface section supports the following operations:
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Each of these operations (between the local microprocessor and the Framer IC) is discussed in detail,
throughout this data sheet.
The Framer supports the following microprocessors/microcontrollers with a minimum amount of glue logic.
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The type of microprocessor/microcontroller to interface to the Framer is specified by tying the μPTYPE[2:0]
pins to the appropriate level. Table 1, lists the values for μPTYPE[2:0] and the corresponding µP/µC types.
The behavior of some of the pins, associated with the Microprocessor Interface, depends upon the value that
the user has applied to the PType[2:0] input pins. The next sections present a detailed discussion on the role of
each of these pins, and how to configure the Framer to interface to each of these types of Microprocessors.
The Framer connects to the Microcontroller as if it were external memory. The microcontroller can read or write
to two different storage elements in the Framer:
1.0 MICROPROCESSOR INTERFACE BLOCK
Communicates through a 7 bit address bus (4 bit for one framer) and an 8 bit data bus.
Supports DMA read/write data interface
Supports burst transfers
Supports Programmed I/O read and write, wait cycle extended with READY/DTACK
Channel Selection
Writing configuration data into the Framer on-chip (addressable) registers
Writing outbound PMDL (Path Maintenance Data Link) messages into the Transmit LAPD Message buffer of
the Framer
Generation of Interrupt Requests to the µP
Servicing Interrupt Requests from the Framer
Monitoring the system's health by periodically reading the on-chip Performance Monitor registers
Reading inbound PMDL Messages from the Receive LAPD Message Buffer of the Framer
Intel 8051, 80C188, x86, i960
Motorola 68HC11, 68K
MIPS 3051/52
PowerPC 403
μ
PTYPE[2:0] I
T
ABLE
000
001
010
100
101
011
NPUT
3: µC/µP S
L
EVELS
33
ELECTION
C
68HC11, 8051, 80C188
Motorola 68000 Family
ORRESPONDING
IDT3051/52 (MIPS)
IBM PowerPC 403
Intel x86 Family
Intel I960
T
ABLE
μ
C/
μ
P
OCTAL T1/E1/J1 FRAMER
XRT84L38