XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 397

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The table below shows configurations of the Signaling Change Interrupt Enable bit of the Framer Interrupt
Enable Register.
FRAMER INTERRUPT ENABLE REGISTER (FIER) (INDIRECT ADDRESS = 0XNAH, 0X05H)
The table below shows configurations of the T1/E1 Framer Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
When these interrupt enable bits are set and the signaling information received is changed, the E1 Receive
Framer block will set the Signaling Updated status bit of the Framer Interrupt Status Register (FISR) to one.
This status indicator is valid until the Framer Interrupt Status Register is read. Reading this register clears the
associated interrupt if Reset-Upon-Read is selected in Interrupt Control Register (ICR). Otherwise, a write-to-
clear operation by the microprocessor is required to reset these status indicators.
The table below shows the Signaling Update status bits of the Framer Interrupt Status Register.
FRAMER INTERRUPT STATUS REGISTER (FISR) (INDIRECT ADDRESS = 0XNAH, 0X04H)
Now, there is only one problem remains. Since there are thirty two DS0 channels in E1, how do we know
signaling information of which channel is changed?
To solve this problem, the XRT84L38 provides three 8-bit Signaling Change Registers to indicate the
channel(s) which signaling data change had occurred over the last E1 multi-frame period. Each bit of the
Signaling Change Registers represents one timeslot of the E1 frame. If any particular bit is zero, it means there
is no change of signaling data occurred in that particular timeslot over the last E1 multi-frame period. If any
particular bit is one, it means there is change of signaling data occurred over the last E1 multi-frame period.
N
N
N
UMBER
UMBER
UMBER
B
B
B
5
1
5
IT
IT
IT
Signaling Updated
Signaling Change
Interrupt Enable
Interrupt Enable
T1/E1 Framer
B
B
B
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
IT
IT
IT
R/W
R/W
WC
T
T
T
YPE
YPE
YPE
0 - The Signaling Update interrupt is disabled.
1 - The Signaling Update interrupt is enabled.
0 - Every interrupt generated by the Framer Interrupt Status Register
(FISR) is disabled.
1 - Every interrupt generated by the Framer Interrupt Status Register
(FISR) is enabled.
0 - There is no change of signaling information in the incoming E1 payload
data.
1 - There is change of signaling information in the incoming E1 payload
data.
377
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38