XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 236

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Line Clock and the Receive Serial Clock are coming from different timing sources, the Slip Buffer will gradually
fill or empty. If the elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties and a
read occurs, then a full frame of data will be repeated and a status bit will be updated. If the buffer fills and a
write comes, then a full frame of data will be deleted and another status bit will be set. A detailed description of
the Elastic Buffer can be found in later sections. In this mode, the Receive Single-Frame Synchronization
signal can be either input or output depending on the settings of the Slip Buffer Receive Synchronization
Direction bit of the Slip Buffer Control Register.
If the Slip Buffer is put into a FIFO mode, it is acting like a standard First-In-First-Out storage. A fixed READ
and WRITE latency is maintained in a programmable fashion controlled by the FIFO Latency Register
(FIFOLR). The local Terminal Equipment supplies a 1.544MHz clock to the Receive Serial Clock pin to latch
the Receive Payload Data out from the FIFO. However, it is the responsibility of the user to phase lock the
input Receive Serial Clock to the Recovered Receive Line Clock to avoid either over-run or under-run of the
FIFO. In this mode, the Receive Single-Frame Synchronization signal can be either input or output depending
on the settings of the Slip Buffer Receive Synchronization Direction bit of the Slip Buffer Control Register.
The following table summaries the input or output nature of the Receive Serial Clock and Receive Single-
Frame Synchronization signals for different Slip Buffer settings.
T
ABLE
R
Slip Buffer Acts as FIFO
ECEIVE
Slip Buffer Bypassed
Slip Buffer Enabled
42: T
T
IMING
HE
R
S
ECEIVE
OURCE
S
ERIAL
C
R
LOCK AND
X
S
Output
Input
Input
ER
C
LK
_
N
R
S
ECEIVE
LIP
B
UFFER SETTINGS
S
S
LIP
216
INGLE
B
UFFER
D
IRECTION
-F
RAME
Output
Output
Output
S
YNCHRONIZATION
B
S
IT
YNCHRONIZATION SIGNALS FOR DIFFERENT
= 0
R
X
S
YNC
S
LIP
_
N
B
UFFER
D
IRECTION
Output
S
Input
Input
YNCHRONIZATION
B
IT
REV. 1.0.1
= 1