XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 424

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The table below shows configurations of the HDLC Controller Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
When these interrupt enable bits are set and the MOS message is transmitted to the data link channel, the
LAPD Controller changes the Transmit Start of Transfer and Transmit End of Transfer status bits of the Data
Link Status Register (DLSR). These two status indicators are valid until the Data Link Status Register is read.
Reading these register clears the associated interrupt if Reset Upon Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Transmit Start of Transfer and Transmit End of Transfer status bits of the Data Link
Status Register.
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
13.1.4.2.6
A one is then written into the LAPD enable bit of Data Link Control Register, which sets the transmitter to
Message-Oriented mode and kicks off the transmission process. The LAPD controller latches these control bits
of the Data Link Control Register and send a Transmit Start of Transfer interrupt (TxSOT) to the
microprocessor to indicate that an MOS message will be send.
The LAPD transmitter will then transmit the open flag character (01111110) in the data link bit position first
followed by the entire message. If the message is longer than 96 bytes or more than one full block of data are
to be transmitted, the alternating buffer usage approach will provide more adequate time to allow the writing of
the message in the Ping-Pong buffers without overwriting good data in the transmitting buffer or repeating data
because it was written too late. User must fill in data fast enough in Ping-Pong buffer concatenation scenario to
avoid automatic flag insertion between two blocks of data that will cause far-end FCS errors.
After the entire MOS message is sent, the LAPD Controller generates the Transmit End of Transfer (TxEOT)
interrupt to the microprocessor indicating that the MOS message transmission is over.
The table below shows configurations of the LAPD Enable bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
N
N
N
UMBER
UMBER
UMBER
B
B
B
3
6
4
0
IT
IT
IT
HDLC Controller
Transmit Start of
Interrupt Enable
Transmit End of
LAPD Enable
Step 6: MOS message transmission
B
B
B
Transfer
Transfer
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
RUR /
IT
IT
IT
R/W
R/W
WC
WC
T
T
T
YPE
YPE
YPE
0 - Every interrupt generated by the HDLC Controller is disabled.
1 - Every interrupt generated by the HDLC Controller is enabled.
0 - There is no data link message to be sent to the data link channel.
1 - The HDLC Controller will send a data link message to the data link
channel.
0 - No data link message was sent to the data link channel.
1 - The HDLC Controller finished sending a data link message to the data
link channel.
0 - The Transmit HDLC Controller will send out Bit-Oriented Signaling
(BOS) message.
1 - The Transmit HDLC Controller will send out LAPD protocol or so-called
Message-Oriented Signaling (MOS) message.
404
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
REV. 1.0.1