XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 374

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The table below shows configurations of the CAS Selection [1:0] bit of the Framing Select Register (FSR).
FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H)
11.2.4
In E1 mode, the Frame Alignment Signal (FAS) pattern of "0011011" contained in bit 2 to 8 of every other frame
(called FAS frame) are used to identify the frame boundaries. In addition, bit 2 of the non-FAS frames is fixed to
"1" to prevent simulation of the FAS frames.
In the non-FAS frames, bit 1 is used to transmit the 6-bit CRC-4 multi-frame alignment signal of "001011" and
two E bits. The 6-bit CRC-4 multi-frame alignment signal is used to identify the CRC-4 multi-frame boundaries.
The A bit at bit 3 of non-FAS frame is used as remote yellow alarm indication. When the A bit is "0", it denotes
undistributed operation of the framer. When the A bit is "1", it denotes yellow alarm condition.
The framing alignment bits include the FAS pattern, the CRC-4 multi-frame alignment bits and the A bit. Under
default condition, the XRT84L38 can generate these framing alignment bits internally.
At the same time, the users can generate the framing alignment bits externally and insert them into the framer
through the Transmit Serial Data Input Interface block via the TxSer_n pin. It is the user's responsibility to
maintain the accuracy and integrity of the framing alignment bits. The user also has to make sure that the
framing alignment bits are inserted into the framer at right position and right timing. However, this option is only
available when the XRT84L38 is configured to run at a normal back-plane rate of 2.048Mbit/s in E1 mode.
The Framing Bit Source Select bit of the Synchronization MUX Register (SMR) controls source of the framing
alignment bit. The table below shows configurations of the Framing Bit Source Select bit of the Synchronization
MUX Register (SMR).
SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H)
N
N
UMBER
UMBER
B
5-4
B
0
IT
IT
How to configure the framer to input the framing alignment bits from different sources
Framing Bit Source
CAS Selection bit
B
B
IT
IT
N
N
AME
AME
B
B
IT
IT
R/W
R/W
T
T
YPE
YPE
These Read/Write bit fields allow the user to enable searching of CAS
Multi-frame alignment and determine which algorithm of the two are used
for locking the CAS Multi-frame alignment pattern.
00 - Searching of CAS Multi-frame alignment is disabled. The XRT84L38
framer will not search for CAS Multi-frame alignment and thus will not
declare CAS Multi-frame synchronization. No Receive CAS Multi-frame
Synchronization (RxCRCMsync_n) pulse will be generated by the framer.
01 - Searching of CAS Multi-frame alignment is enabled. The XRT84L38
will search for and declare CAS Multi-frame synchronization using Algo-
rithm 1.
10 - Searching of CAS Multi-frame alignment is enabled. The XRT84L38
will search for and declare CAS Multi-frame synchronization using Algo-
rithm 2 (G.732).
11 - Searching of CAS Multi-frame alignment is disabled. The XRT84L38
framer will not search for CAS Multi-frame alignment and thus will not
declare CAS Multi-frame synchronization. No Receive CAS Multi-frame
Synchronization (RxCRCMsync_n) pulse will be generated by the framer.
This READ/WRITE bit-field permits the user to determine where the fram-
ing alignment bits should be inserted.
0 - The framing alignment bits are generated and inserted by the framer
internally.
1 - If the framer is operating in normal 2.048Mbit/s mode, the framing align-
ment bits are passed through from the Transmit Serial Data Input Interface
block via the TxSer_n pin.
354
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
REV. 1.0.1