XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 248

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
•
•
The Receive Back-plane interface is pumping out data through RxSer_n at an E1 equivalent data rate of
2.048Mbit/s. The local Terminal Equipment supplies a free-running 2.048MHz clock to the Receive Serial
Clock input. The Receive High-speed Back-plane Interface of the framer then sends out serial data at rising
edge of the Receive Serial Clock. The local Terminal Equipment samples the serial data at falling edge of the
clock.
The Terminal Equipment take in data grouped in 256-bit frame 8000 times every second. Each frame consists
of thirty-two octets as in E1. The Receive High-speed Back-plane Interface maps a 193-bit T1 frame into this
256-bit format as described below:
The mapping of T1 frame into E1 framing format is shown in the table below.
The Receive Single-frame Synchronization input signal (RxSync_n) should pulse HIGH at the beginning of the
256-bit frame indicating start of the frame. By sampling the HIGH pulse of the Receive Single-frame
Synchronization signal, the framer can identity the beginning of a DS1 frame and start pumping payload data
out.
1. The F-bit is mapped into MSB of the first E1 Time-slot. The framer will insert seven "don't care" bits to the
2. Payload data of T1 Time-slot 0, 1 and 2 are mapped into E1 Time-slot 1, 2 and 3.
3. The Receive High-speed Back-plane Interface will stuff E1 Time-slot 4 with eight "don't care" bits that
4. Following the same rules of Step 2 and 3, the Receive High-speed Back-plane Interface maps every three
Receive Time-slot Indication clock (RxTSClk_n)
Receive Time Slot indicator bits (RxTSb[4:0]_n)
rest of the first octet that would be ignored by the local Terminal Equipment.
would be ignored by the local Terminal Equipment.
time-slots of T1 payload data into four E1 time-slots.
T1
E1
T1
E1
T1
E1
T1
E1
Don't Care Bits
Don't Care Bits
Don't Care Bits
TS16
TS24
F-Bit
TS0
TS8
T
ABLE
45: T
TS12
TS17
TS18
TS25
TS0
TS1
TS6
TS9
HE MAPPING OF
TS10
TS13
TS18
TS19
TS26
TS1
TS2
TS7
T1
228
TS14
TS19
TS20
TS27
TS11
FRAME INTO
TS2
TS3
TS8
Don't Care Bits
Don't Care Bits
Don't Care Bits
Don't Care Bits
E1
TS12
TS20
TS28
TS4
FRAMING FORMAT
TS13
TS15
TS21
TS21
TS29
TS3
TS5
TS9
TS10
TS14
TS16
TS22
TS22
TS30
TS4
TS6
REV. 1.0.1
TS11
TS15
TS17
TS23
TS23
TS31
TS5
TS7