CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 58

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 83. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W]
Endpoint Data Buffers
The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long. The reset values of
the Endpoint Data Registers are unknown. Unlike past enCoRe parts the USB data buffers are only accessible in the I/O space of the
processor.
Table 84. Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
Note When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the
EP1MODE registers, respectively (if both writes occur in the same clock cycle). This is because the design employs only one
common ‘update’ signal for both EP1MODE and EP2MODE registers. Thus, when SIE writes to the EP1MODE register, the
update signal is set and this prevents firmware writes to EP2MODE register. SIE writes to the endpoint mode registers have
higher priority than firmware writes. This mode register write block situation can put the endpoints in incorrect modes. Firmware
must read the EP1/2MODE registers immediately following a firmware write and rewrite if the value read is incorrect
Bit #
Field
Read/Write
Default
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
Stall
When this bit is set the SIE stalls an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE stalls an IN
packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes
Reserved
NAK Int Enable
This bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
Unlike enCoRe, CYRF69213 family members do not generate an endpoint interrupt under these conditions unless
this bit is set
0 = Disable interrupt on NAK’d transactions
1 = Enable interrupt on NAK’d transaction
ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that com-
pletes with an ACK packet
This bit is cleared by any writes to the register
0 = The transaction does not complete with an ACK
1 = The transaction completes with an ACK
Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The
mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a
result of host packets to the endpoint.
Unknown
Stall
R/W
R/W
7
0
7
Reserved
Unknown
R/W
R/W
6
0
6
Unknown
NAK Int
Enable
R/W
R/W
5
0
5
Endpoint 0 Data Buffer [7:0]
R/C (Note 3)
Transaction
Unknown
ACK’d
R/W
4
0
4
Unknown
R/W
R/W
3
0
3
Unknown
R/W
R/W
2
0
2
Mode[3:0]
Unknown
R/W
R/W
1
0
1
CYRF69213
Unknown
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