CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 32

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Document #: 001-07552 Rev. *D
Power on Reset
POR occurs every time the power to the device is switched on.
POR is released when the supply is typically 2.6V for the
upward supply transition, with typically 50 mV of hysteresis
during the power on transient. Bit 4 of the System Status and
Control Register (CPU_SCR) is set to record this event (the
register contents are set to 00010000 by the POR). After a
POR, the microprocessor is held off for approximately 20 ms
for the V
instruction at address 0x00 in the Flash. If the V
drops below the POR downward supply trip point, POR is
reasserted. The V
4V in 0 to 200 ms.
Important The PORS status bit is set at POR and can only be
cleared by the user. It cannot be set by firmware.
Watchdog Timer Reset
The user has the option to enable the WDT. The WDT is
enabled by clearing the PORS bit. When the PORS bit is
cleared, the WDT cannot be disabled. The only exception to
this is if a POR event takes place, which disables the WDT.
Table 42. Reset Watchdog Timer (RESWDT) [0xE3] [W]
Sleep Mode
The CPU can only be put to sleep by the firmware. This is
accomplished by setting the Sleep bit in the System Status and
Control Register (CPU_SCR). This stops the CPU from
executing instructions, and the CPU remains asleep until an
interrupt comes pending, or there is a reset event (either a
Power on Reset, or a Watchdog Timer Reset).
The Low voltage Detection circuit (LVD) drops into fully
functional power reduced states, and the latency for the LVD
is increased. The actual latency can be traded against power
consumption by changing the Sleep Duty Cycle field of the
ECO_TR Register.
The Internal 32 kHz Low speed Oscillator remains running.
Prior to entering suspend mode, firmware can optionally
configure the 32 kHz Low speed Oscillator to operate in a low
power mode to help reduce the overall power consumption
(using Bit 7,
however, the trade off is that the 32 kHz Low speed Oscillator
is less accurate.
All interrupts remain active. Only the occurrence of an interrupt
wakes the part from sleep. The Stop bit in the System Status
and Control Register (CPU_SCR) must be cleared for a part
to resume out of sleep. The Global Interrupt Enable bit of the
CPU Flags Register (CPU_F) does not have any effect. Any
unmasked interrupt wakes the system up. As a result, any
interrupts not intended for waking must be disabled through
the Interrupt Mask Registers.
Bit #
Field
Read/Write
Default
Any write to this register clears Watchdog Timer, a write of 0x38 also clears the Sleep Timer
Bits 7:0
CC
Reset Watchdog Timer [7:0]
Table
supply to stabilize before executing the first
CC
35). This helps save approximately 5 μ A;
W
7
0
supply needs to ramp linearly from 0 to
W
6
0
W
5
0
CC
voltage
Reset Watchdog Timer [7:0]
W
4
0
The sleep timer is used to generate the sleep time period and
the Watchdog time period. The sleep timer is clocked by the
Internal 32 kHz Low power Oscillator system clock. The user
can program the sleep time period using the Sleep Timer bits
of the OSC_CR0 Register
elapses (sleep timer overflows), an interrupt to the Sleep Timer
Interrupt Vector is generated.
The Watchdog Timer period is automatically set to be three
counts of the Sleep Timer overflows. This represents between
two and three sleep intervals depending on the count in the
Sleep Timer at the previous WDT clear. When this timer
reaches three, a WDR is generated.
The user can either clear the WDT, or the WDT and the Sleep
Timer. Whenever the user writes to the Reset WDT Register
(RES_WDT), the WDT is cleared. If the data that is written is
the hex value 0x38, the Sleep Timer is also cleared at the
same time.
When the CPU enters sleep mode the CPUCLK Select (Bit 1,
Table
lator recovery time is three clock cycles of the Internal 32 kHz
Low power Oscillator. The Internal 24 MHz Oscillator restarts
immediately on exiting Sleep mode. If an external clock is
used, firmware needs to switch the clock source for the CPU.
On exiting sleep mode, when the clock is stable and the delay
time has expired, the instruction immediately following the
sleep instruction is executed before the interrupt service
routine (if enabled).
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintaining
very low average power consumption. The Sleep interrupt
may also be used to provide periodic interrupts during non
sleep modes.
Sleep Sequence
The SLEEP bit is an input into the sleep logic circuit. This
circuit is designed to sequence the device into and out of the
hardware sleep state. The hardware sequence to put the
device to sleep is shown in
1. Firmware sets the SLEEP bit in the CPU_SCR0 register.
The Bus Request (BRQ) signal to the CPU is immediately
asserted. This is a request by the system to halt CPU
operation at an instruction boundary. The CPU samples
BRQ on the positive edge of CPUCLK.
36) is forced to the Internal Oscillator. The internal oscil-
W
3
0
W
2
0
Figure 12
(Table
37). When the sleep time
and is defined as follows.
W
1
0
CYRF69213
Page 32 of 77
W
0
0
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