CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 26

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 36. CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
Bit 7
Bit 6
Bit 5
Bits 4:1
Bit 0
Note The CPU speed selection is configured using the OSC_CR0 Register
Reserved
USB CLK/2 Disable
This bit only affects the USBCLK when the source is the external clock. When the USBCLK source is the Internal
24-MHz Oscillator, the divide by two is always enabled
0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24 MHz Oscillator is used, or
when the external source is used with a 24 MHz clock
1 = USBCLK is undivided. Use this setting only with a 12 MHz external clock
USB CLK Select
This bit controls the clock source for the USB SIE
0 = Internal 24 MHz Oscillator. With the presence of USB traffic, the Internal 24 MHz Oscillator can be trimmed to meet
the USB requirement of 1.5% tolerance (see
1 = External clock—Internal Oscillator is not trimmed to USB traffic.
Proper USB SIE operation requires a 12 MHz or 24 MHz clock accurate to <1.5%
Reserved
CPU CLK Select
0 = Internal 24 MHz Oscillator
1 = External clock—External clock at CLKIN (P0.0) pin
Reserved
7
–
0
USB CLK/2
Disable
R/W
6
0
USB CLK
Select
R/W
5
0
Table
38)
4
–
0
(Table
3
–
0
37)
Reserved
2
–
0
1
–
0
CYRF69213
Page 26 of 77
CPUCLK Se-
R/W
lect
0
0
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