CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 37

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 47. P1 Data Register (P1DATA) [0x01] [R/W]
Table 48. P2 Data Register (P2DATA) [0x02] [R/W]
GPIO Port Configuration
All the GPIO configuration registers have common configuration
controls. The following are the bit definitions of the GPIO config-
uration registers.
Int Enable
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the pin
is configured for input or output. All interrupts are edge sensitive,
however for any interrupt that is shared by multiple sources (that
is, Ports 2, 3, and 4) all inputs must be deasserted before a new
interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the interrupt
on the pin and then to generate the interrupt by driving the appro-
priate pin state. This is useful in test and may have value in appli-
cations as well.
Int Act Low
When set, the corresponding interrupt is active on the falling
edge.
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins
Bit 7
Bits 6:3
Bit 2
Bits 1:0
Bit #
Field
Read/Write
Default
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins
Bits 7:2
Bits 1:0
P1.7 Data
P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
In addition to their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternative function as the SPI
interface pins. To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register
The use of the pins as the P1.6–P1.3 GPIOs and the alternative functions exist in all the CYRF69213 parts
P1.2/VREG
This pin is used as the regulator output. The 3.3V VREG output must be enabled by setting Bit 0 of VREGCR register
(Table
P1.1–P1.0/D– and D+
When USB mode is disabled (Bit 7 in
and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins, respectively.
If the USB Force State bit (Bit 0 in
D– and D+ bits
Reserved Data [7:2]
P2 Data [1:0]
P1.7
R/W
79). A 1 mF min, 2 mF max capacitor is required on VREG output.
7
0
7
0
-
P1.6/SMISO P1.5/SMOSI
R/W
6
0
-
6
0
Table
R/W
5
0
-
5
0
Table 80
Reserved
78) is set, the state of the D– and D+ pins can be controlled by writing to the
is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0
P1.4/SCLK
4
0
R/W
-
4
0
When clear, the corresponding interrupt is active on the rising
edge.
TTL Thresh
When set, the input has TTL threshold. When clear, the input has
standard CMOS threshold.
High Sink
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CYRF69213, only the P1.7–P1.3 have 50 mA sink drive
capability. Other pins have 8 mA sink drive capability.
Open Drain
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is set,
the pin is in high impedance state. If the corresponding bit in the
Port Data Register is clear, the pin is driven low.
When clear, the output is driven LOW or HIGH.
P1.3/SSEL
3
0
-
R/W
3
0
P1.2/VREG
2
0
-
R/W
2
0
R/W
P1.1/D–
1
0
R/W
(Table
P2.1–P2.0
1
0
CYRF69213
55)
Page 37 of 77
R/W
0
0
P1.0/D+
R/W
0
0
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