CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 31

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 41. System Status and Control Register (CPU_SCR) [0xFF] [R/W]
Note
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
T
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2:1
Bit 0
3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware
he bits of the CPU_SCR register are used to convey status and control of events for various functions of an CYRF69213 device
GIES
The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit,
which was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now
readable. When this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that
the microprocessor services interrupts
0 = Global interrupts disabled
1 = Global interrupt enabled
Reserved
WDRS
The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine
the type of reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
PORS
The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the
type of reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events does not occur until this bit is cleared)
SLEEP
Set by the user to enable CPU sleep state. CPU remains in sleep mode until any interrupt is pending. The Sleep bit is
covered in more detail in the
0 = Normal operation
1 = Sleep
Reserved
STOP
This bit is set by the user to halt the CPU. The CPU remains halted until a reset (WDR, POR, or external reset) has
taken place. If an application wants to stop code execution until a reset, the preferred method would be to use the
HALT instruction rather than writing to this bit
0 = Normal CPU operation
1 = CPU is halted (not recommended)
GIES
R
7
0
Reserved
6
–
0
Sleep Mode
WDRS
R/C
5
0
[3]
section
PORS
R/C
4
1
[3]
Sleep
R/W
3
0
–
0
2
Reserved
–
0
1
CYRF69213
Page 31 of 77
Stop
R/W
0
0
[+] Feedback