CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 49

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the CYRF69213 devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually. The registers also provide
a mechanism by which a user may clear all pending and posted
interrupts, or clear individual posted or pending interrupts.
The following table lists all interrupts and the priorities that are
available in the CYRF69213.
Table 69. Interrupt Numbers, Priorities, Vectors
Document #: 001-07552 Rev. *D
Interrupt
Priority
10
12
13
14
15
16
11
0
1
2
3
4
5
6
7
8
9
GPIO, etc.)
Interrupt
Source
(Timer,
Interrupt
Address
000Ch
001Ch
002Ch
003Ch
0000h
0004h
0008h
0010h
0014h
0018h
0020h
0024h
0028h
0030h
0034h
0038h
0040h
Reset
POR/LVD
INT0
SPI Transmitter Empty
SPI Receiver Full
GPIO Port 0
GPIO Port 1
INT1
EP0
EP1
EP2
USB Reset
USB Active
1 ms Interval timer
Programmable Interval Timer
Reserved
Reserved
1
INT_CLRx Write
Interrupt Taken
D
or
R
Q
Name
Figure 19. Interrupt Controller Block Diagram
Mask Bit Setting
Interrupt
INT_MSKx
Posted
Interrupt
Pending
Table 69. Interrupt Numbers, Priorities, Vectors (continued)
Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in
remains posted until the interrupt is taken or until it is cleared by
writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It simply prevents a
posted interrupt from becoming pending.
Nested interrupts can be accomplished by re-enabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register.
A block diagram of the CYRF69213 Interrupt Controller is shown
in
Interrupt
Priority
Figure
Encoder
Priority
17
18
19
20
21
22
23
24
25
19.
Interrupt
Address
004Ch
005Ch
0044h
0048h
0050h
0054h
0058h
0060h
0064h
CPU_F[0]
Interrupt Vector
GIE
Figure 19
16-bit Free Running Timer Wrap
INT2
Reserved
GPIO Port 2
Reserved
Reserved
Reserved
Reserved
Sleep Timer
clocking in a ‘1’. The interrupt
Interrupt
Request
Name
M8C Core
CYRF69213
Page 49 of 77
[+] Feedback