CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 51

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 71. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Table 72. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) are used to enable
the individual interrupt sources’ ability to create pending inter-
rupts.
There
INT_MSK1, INT_MSK2, and INT_MSK3), which may be referred
to in general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents a posted interrupt from becoming a pending
interrupt (input to the priority encoder). However, an interrupt can
still post even if its mask bit is zero. All INT_MSKx bits are
independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that becomes a pending
interrupt.
Table 73. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt
Bit 7
Bit #
Field
Read/Write
Default
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT (Bit
7 of the INT_MSK3 Register) posts the corresponding hardware interrupt
Bits 7,6,5,3,0Reserved
Bit #
Field
Read/Write
Default
Bit 7
Bits 6:0
are
Reserved
Enable Software Interrupt (ENSWINT)
0 = Disable. Writing 0’s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear
1 = Enable. Writing 1’s to an INT_CLRx register, when ENSWINT is set, causes the corresponding interrupt to post
Reserved
four
ENSWINT
Reserved
Reserved
R/W
R/W
R/W
Interrupt
7
0
7
0
7
0
Prog Interval
Mask
Reserved
Timer
R/W
R/W
6
0
6
0
6
–
0
Registers
1 ms Timer
Reserved
R/W
R/W
5
0
5
0
5
–
0
(INT_MSK0,
GPIO Port 2
USB Active
R/W
R/W
4
0
4
0
4
–
0
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When is cleared, writing 1's to
an INT_CLRx register has no effect. However, writing 0's to an
INT_CLRx register, when ENSWINT is cleared, causes the
corresponding interrupt to clear. If the ENSWINT bit is set, any
0’s written to the INT_CLRx registers are ignored. However, 1’s
written to an INT_CLRx register, while ENSWINT is set, causes
an interrupt to post for the corresponding interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level interac-
tions that are sometimes necessary to create a hardware-only
interrupt.
USB Reset
Reserved
Reserved
R/W
R/W
3
0
3
0
3
–
0
USB EP2
R/W
INT2
R/W
2
0
2
0
2
–
0
USB EP1
Counter
16-bit
Wrap
R/W
R/W
1
0
1
0
1
–
0
CYRF69213
Page 51 of 77
USB EP0
Reserved
R/W
R/W
0
0
0
0
0
–
0
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