CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 54

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

USB Transceiver
USB Transceiver Configuration
Table 78. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
VREG Control
Table 79. VREG Control Register (VREGCR) [0x73] [R/W]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
Bit 7
Bits 6:1
Bit 0
Note The USB transceiver has a dedicated 3.3V regulator for USB signalling purposes and to provide for the 1.5K D– pull up.
Unlike the other 3.3V regulator, this regulator cannot be controlled/accessed by firmware. When the device is suspended, this
regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D– line is pulled up
to 5V through an alternate 6.5K resistor. During wakeup following a suspend, the band gap and the regulator are switched on
in any order. Under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator
and the band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the D– line. The host can
misinterpret this as a deattach condition. This condition, although rare, can be avoided by keeping the bandgap circuitry enabled
during sleep. This is achieved by setting the ‘No Buzz’ bit, bit[5] in the OSC_CR0 register. This is an issue only if the device is
put to sleep during a bus reset condition
Bit #
Field
Read/Write
Default
Bits 7:2
Bit 1
Bit 0
Note Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and provide
the alternate voltage
USB Pull up Enable
0 = Disable the pull up resistor on D–
1 = Enable the pull up resistor on D–. This pull up is to V
3.3V when VREG is enabled. This bit should be cleared in sleep mode.
Reserved
USB Force State
This bit allows the state of the USB I/O pins DP and D+ to be forced to a state while USB is enabled
0 = Disable USB Force State
1 = Enable USB Force State. Allows the D– and D+ pins to be controlled by P1.1 and P1.0 respectively when the
USBIO is in USB mode. Refer to
Reserved
Keep Alive
Keep Alive when set allows the voltage regulator to source up to 20 µA of current when voltage regulator is dis-
abled, P12CR[0],P12CR[7] should be cleared.
0 = Disabled
1 = Enabled
VREG Enable
This bit turns on the 3.3V voltage regulator. The voltage regulator only functions within specifications when V
above 4.35V. This block should not be enabled when V
occurs if it is enabled below 4.35V
0 = Disable the 3.3V voltage regulator output on the VREG/P1.2 pin
1 = Enable the 3.3V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled
USB Pull up
Enable
R/W
7
0
7
–
0
6
–
0
6
–
0
Table 47
5
–
0
5
–
0
Reserved
for more information
4
–
0
4
–
0
Reserved
CC
CC
is below 4.35V—although no damage or irregularities
IF VREG is not enabled or to the internally generated
3
–
0
3
–
0
2
–
0
2
–
0
Keep Alive
R/W
1
–
0
1
0
CYRF69213
USB Force
VREG En-
State
Page 54 of 77
R/W
able
R/W
0
0
0
0
CC
is
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