CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 40

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 52. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Table 53. P1.1/D– Configuration (P11CR) [0x0E] [R/W]
Table 54. P1.2 Configuration (P12CR) [0x0F] [R/W]
Document #: 001-07552 Rev. *D
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See
register have any effect on the P1.0 pin
Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high
Bit 1
Bit 0
Bit #
Field
Read/Write
Default
This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See
register have any effect on the P1.1 pin. When USB is disabled, the 5 Kohm pull up resistor on this pin can be enabled by the
PS/2 Pull up Enable bit of the P10CR Register
Bit 0
Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at V
Bit #
Field
Read/Write
Default
This register controls the operation of the P1.2
Bit 7
PS/2 Pull up Enable
0 = Disable the 5 Kohm pull up resistors
1 = Enable 5 Kohm pull up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as
a PS2 style interface
This bit enables the output on P1.0/D+. This bit should be cleared in sleep mode.
This bit enables the output on P1.1/D-. This bit should be cleared in sleep mode.
CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
CLK Output
Reserved
R/W
7
–
0
7
0
Int Enable
Int Enable
Table 80
Table 80
R/W
R/W
6
0
6
0
for information on enabling USB. When USB is enabled, none of the controls in this
for information on enabling USB. When USB is enabled, none of the controls in this
Int Act Low
Int Act Low TTL Thresh-
R/W
R/W
(Table
5
0
5
0
52)
R/W
old
4
–
0
4
0
Reserved
Reserved
3
–
0
3
–
0
Open Drain
Open Drain
OL3
R/W
R/W
2
0
2
0
Pull up En-
Reserved
able
R/W
1
–
0
1
0
CYRF69213
Output En-
Output En-
Page 40 of 77
able
R/W
able
R/W
0
0
0
0
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