HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 969

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.2
21.2.1
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial
state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is
initialized by the TRST pin or in the TAP Test-Logic-Reset state. When this register is written to
from the H-UDI, writing is possible regardless of the CPU mode. However, if a read is performed
by the CPU while writing is in progress, it may not be possible to read the correct value. In this
case, SDIR should be read twice, and then read again if the read values do not match. Operation is
undefined if a reserved command is set in this register.
SH7750, SH7750S:
Bits 15 to 12—Test Instruction Bits (TI3−TI0)
Bit 15: TI3
0
1
Initial value:
Initial value:
Register Descriptions
Instruction Register (SDIR)
R/W:
R/W:
Bit 14: TI2
0
1
0
1
Bit:
Bit:
TI3
15
—
R
R
1
7
1
Bit 13: TI1
—
0
1
0
1
0
1
TI2
14
—
R
R
1
6
1
Section 21 High-performance User Debug Interface (H-UDI)
TI1
13
—
R
R
1
5
1
Bit 12: TI0
—
—
0
1
—
—
—
0
1
TI0
12
—
R
R
1
4
1
Rev.7.00 Oct. 10, 2008 Page 883 of 1074
Description
Reserved
Reserved
H-UDI reset negate
H-UDI reset assert
Reserved
H-UDI interrupt
Reserved
Reserved
Bypass mode
11
—
—
R
R
1
3
1
10
—
—
R
R
1
2
1
REJ09B0366-0700
—
—
R
R
9
1
1
1
(Initial value)
—
—
R
R
8
1
0
1