HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 955

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4. When operand access (address only) is set as a break condition, the address of the instruction
5. When operand access (address + data) is set as a break condition, execution of the instruction
20.3.8
When channel A match and channel B match timings are close together, a sequential break may
not be guaranteed. Rules relating to the guaranteed range are given below.
1. Instruction access matches on both channel A and channel B
instructions ahead of the branch instruction (when the branch is not made). In this case, the PC
value saved to SPC is the address of the branch destination (when the branch is made) or the
instruction following the delay slot instruction (when the branch is not made).
to be executed after the instruction at which the condition match occurred is saved to SPC.
The instruction at which the condition match occurred is executed, and a user break interrupt
occurs before the following instruction is executed.
at which the condition match occurred is completed. A user break interrupt is generated before
execution of instructions from one instruction later to four instructions later. It is not possible
to specify at which instruction, from one later to four later, the interrupt will be generated. The
start address of the instruction after the instruction for which execution is completed at the
point at which user break interrupt handling is started is saved to SPC. If an instruction
between one instruction later and four instructions later causes another exception, control is
performed as follows. Designating the exception caused by the break as exception 1, and the
exception caused by an instruction between one instruction later and four instructions later as
exception 2, the fact that memory updating and register updating that essentially cannot be
performed by exception 2 cannot be performed is guaranteed irrespective of the existence of
exception 1. The program counter value saved is the address of the first instruction for which
execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump
destination and the value written to the exception register (EXPEVT/INTEVT) is not
guaranteed. However, if exception 2 is from a source not synchronized with an instruction
(external interrupt or peripheral module interrupt), exception 1 is used for the exception jump
destination and the value written to the exception register (EXPEVT/INTEVT).
Instruction B is 0 instructions after
instruction A
Instruction B is 1 instruction after
instruction A
Instruction B is 2 or more instructions
after instruction A
Contiguous A and B Settings for Sequential Conditions
Equivalent to setting the same address. Do not use
this setting.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Rev.7.00 Oct. 10, 2008 Page 869 of 1074
Section 20 User Break Controller (UBC)
REJ09B0366-0700