HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 538

Manufacturer Part Number

HD6417750RF200DV

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

Manufacturer

Renesas Electronics America

SuperH® SH7750r

Core Processor

Connectivity

EBI/EMI, FIFO, SCI, SmartCard

DMA, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.35 V ~ 1.6 V

Oscillator Type

Operating Temperature

-40°C ~ 85°C

Package / Case

208-QFP Exposed Pad, 208-eQFP, 208-HQFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Data Converters

Manufacturer

Part Number:

HD6417750RF200DV

Manufacturer:

Section 13 Bus State Controller (BSC)

Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in

figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and

Tc2 the read data latch cycle.

Rev.7.00 Oct. 10, 2008 Page 452 of 1074

REJ09B0366-0700

(SA: IO ← memory)

(SA: IO → memory)

IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

The DACK is in the high-active setting

For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.17 Basic DRAM Access Timing