HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 391

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.8.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR)
differ from other registers in being more difficult to write to. The procedure for writing to these
registers is given below.
Writing to WTCNT and WTCSR: These registers must be written to with a word transfer
instruction. They cannot be written to with a byte or longword transfer instruction. When writing
to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the
write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the
lower byte containing the write data. This transfer procedure writes the lower byte data to
WTCNT or WTCSR. The write formats are shown in figure 10.3.
10.9
10.9.1
The WDT is used when clearing standby mode by means of an NMI or other interrupt. The
procedure is shown below. (As the WDT does not operate when standby mode is cleared with a
reset, the RESET pin should be held low until the clock stabilizes.)
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby
2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the
WTCNT write
WTCSR write
mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused
when the count overflows.
initial value in the WTCNT counter. Make these settings so that the time until the count
Address: H'FFC0000C
Address: H'FFC00008
Notes on Register Access
Using the WDT
Standby Clearing Procedure
(H'1FC0000C)
(H'1FC00008)
Figure 10.3 Writing to WTCNT and WTCSR
15
15
H'5A
H'A5
Rev.7.00 Oct. 10, 2008 Page 305 of 1074
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Section 10 Clock Oscillation Circuits
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Write data
Write data
REJ09B0366-0700
0
0