HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 57

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.3 Operation........................................................................................................................... 421
Section 14 Direct Memory Access Controller (DMAC)
14.1 Overview........................................................................................................................... 545
14.2 Register Descriptions (SH7750, SH7750S) ...................................................................... 552
14.3 Operation........................................................................................................................... 567
14.4 Examples of Use ............................................................................................................... 602
13.2.14 Refresh Count Register (RFCR) .......................................................................... 420
13.2.15 Notes on Accessing Refresh Control Registers.................................................... 420
13.3.1 Endian/Access Size and Data Alignment............................................................. 421
13.3.2 Areas .................................................................................................................... 433
13.3.3 SRAM Interface ................................................................................................... 438
13.3.4 DRAM Interface .................................................................................................. 447
13.3.5 Synchronous DRAM Interface............................................................................. 465
13.3.6 Burst ROM Interface............................................................................................ 497
13.3.7 PCMCIA Interface ............................................................................................... 500
13.3.8 MPX Interface...................................................................................................... 511
13.3.9 Byte Control SRAM Interface ............................................................................. 529
13.3.10 Waits between Access Cycles.............................................................................. 534
13.3.11 Bus Arbitration..................................................................................................... 536
13.3.12 Master Mode ........................................................................................................ 539
13.3.13 Slave Mode .......................................................................................................... 540
13.3.14 Partial-Sharing Master Mode ............................................................................... 541
13.3.15 Cooperation between Master and Slave ............................................................... 542
13.3.16 Notes on Usage .................................................................................................... 543
14.1.1 Features................................................................................................................ 545
14.1.2 Block Diagram (SH7750, SH7750S) ................................................................... 547
14.1.3 Pin Configuration (SH7750, SH7750S) ............................................................... 549
14.1.4 Register Configuration (SH7750, SH7750S) ....................................................... 550
14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 552
14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 553
14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 554
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 555
14.2.5 DMA Operation Register (DMAOR)................................................................... 564
14.3.1 DMA Transfer Procedure..................................................................................... 567
14.3.2 DMA Transfer Requests ...................................................................................... 569
14.3.3 Channel Priorities................................................................................................. 573
14.3.4 Types of DMA Transfer....................................................................................... 576
14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 585
14.3.6 Ending DMA Transfer ......................................................................................... 599
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