HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 732

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)
DTR.ID[1:0]
00
01
10
11
Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
DMAOR
Bit 9
PR1
0
0
1
1
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in
section 14.2.5, DMA Operation Register (DMAOR)
Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
Rev.7.00 Oct. 10, 2008 Page 646 of 1074
REJ09B0366-0700
63
SZ
61 60 59 58 57 56 55
Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)
R/W
DMAOR
Bit 8
PR0
0
1
0
1
ID
DTR.SZ[2:0] ≠ 101
CH0
CH1
CH2
CH3
MD
Description
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1
CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7
Round robin mode
COUNT
4847
(Reserved)
32 31
DTR.SZ[2:0] = 101
CH4
CH5
CH6
CH7
ADDRESS
(Initial value)
0