HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 889

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.1
This LSI has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port.
18.1.1
The features of the general-purpose I/O port are as follows:
• 20-bit I/O port with input/output direction independently specifiable for each bit
• Pull-up can be specified independently for each bit.
• Interrupt input is possible for 16 of the 20 I/O port bits.
• Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2
The features of the SCI I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCI enabling has not been
• The RxD pin value can be read at all times, allowing break state detection.
• SCK pin control is possible when the I/O port is designated for output and SCI enabling has
• The SCK pin value can be read at all times.
The features of the SCIF I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCIF enabling has not been
• The RxD2 pin value can be read at all times, allowing break state detection.
• CTS2 and RTS2 pin control is possible when the I/O port is designated for output and SCIF
• The CTS2 and RTS2 pin values can be read at all times.
(BCR2).
set. This allows break function transmission.
not been set.
set. This allows break function transmission.
enabling has not been set.
Overview
Features
Section 18 I/O Ports
Rev.7.00 Oct. 10, 2008 Page 803 of 1074
Section 18 I/O Ports
REJ09B0366-0700