HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 27

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
14.5.2 Pins in DDT
Mode
Figure 14.24 System
Configuration in On-
Demand Data Transfer
Mode
•
14.8.3 Transfer
Channel Notification in
DDT Mode
Table 14.16 Function
of BAVL
14.9 Usage Notes
10. [SH7750 Only]
15.1 Overview
TR: Transfer request
signal
Page
605
608
648
653
655
Revision (See Manual for Details)
Figure amended
A25–A0, RAS, CAS, WE, DQMn, CKE
Description amended
Assertion of TR has the following different meanings.
⎯ In normal data transfer mode (channel 0, except channel 0),
Notes amended
7. For DTR format transfer when ID[1:0] = 00, input MD[1:0]
Description amended
When the DMAC is set up for eight-channel external request
acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits
and the simultaneous (on the timing of TDACK assertion)
assertion of ID2 from the BAVL (data bus available) pin are
used to notify the external device of the DMAC channel that is
to be used (see table 14.15).
Table amended
TDACK = High
Newly added
Description amended
The SCI supports a smart card interface. This is a serial
communication function supporting a subset of the ISO/IEC
7816-3 (identification cards) standard. For details, see section
17, Smart Card Interface.
SH7750, SH7750S, SH7750R
and SZ ≠ 101, 110.
TR is asserted, and at the same time the DTR format is
output, two cycles after BAVL is asserted.
Rev.7.00 Oct. 10, 2008 Page xxv of lxxxiv
Function of B B AVL
Bus available
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D63–D0=DTR
Synchronous
DRAM
REJ09B0366-0700
External device