HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 81

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 423
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 424
Table 13.8
Table 13.9
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 427
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment ................. 428
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment ................. 429
Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment ....................... 430
Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment ....................... 431
Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment ......................... 432
Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing... 451
Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address
Table 13.17 Cycles for which Pipeline Access is Possible......................................................... 484
Table 13.18 Relationship between Address and CE when Using PCMCIA Interface ............... 502
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10 Conditions for Transfer between External Memory and an External Device with
Table 14.11 DMAC Pins ............................................................................................................ 636
Table 14.12 DMAC Pins in DDT Mode .................................................................................... 637
Table 14.13 Register Configuration ........................................................................................... 638
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)....................................... 646
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode ............................ 648
BSC Pins ................................................................................................................ 360
BSC Registers ........................................................................................................ 364
External Memory Space Map................................................................................. 366
PCMCIA Interface Features ................................................................................... 368
PCMCIA Support Interfaces .................................................................................. 369
MPX Interface is Selected (Areas 0 to 6) ............................................................... 398
32-Bit External Device/Big-Endian Access and Data Alignment .......................... 425
16-Bit External Device/Big-Endian Access and Data Alignment .......................... 426
Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) ........................... 468
DMAC Pins ............................................................................................................ 549
DMAC Pins in DDT Mode .................................................................................... 550
DMAC Registers .................................................................................................... 550
Selecting External Request Mode with RS Bits ..................................................... 570
Selecting On-Chip Peripheral Module Request Mode with RS Bits ...................... 572
Supported DMA Transfers ..................................................................................... 576
Relationship between DMA Transfer Type, Request Mode, and Bus Mode ......... 582
External Request Transfer Sources and Destinations in Normal DMA Mode ....... 583
External Request Transfer Sources and Destinations in DDT Mode ..................... 584
DACK, and Corresponding Register Settings ........................................................ 602
Rev.7.00 Oct. 10, 2008 Page lxxix of lxxxiv
REJ09B0366-0700