HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 542

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst
mode. By using this address comparator, and also setting RAS down mode specification bit RASD
to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an
access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM
RAS assert time, the refresh cycle must be decreased to or below the maximum value of t
RAS down mode can only be used when DRAM is connected in area 3.
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus request, RAS is negated and the necessary operation
is performed. When DRAM access is resumed after this, since this is the start of RAS down mode,
the operation starts with row address output. Timing charts are shown in figures 13.22 (1) to (4).
Rev.7.00 Oct. 10, 2008 Page 456 of 1074
REJ09B0366-0700
CKIO
A25–A0
CSn
RD/WR
RAS
CAS
D63–D0
(read)
BS
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.21 Burst Access Timing in DRAM EDO Mode
Tr1
r
Tr2
Tc1
c1
Tc2
Tc1
d1
c2
Tc2
Tc1
d2
c3
Tc2
Tc1
d3
Tc2
c4
Tce
d4
Tpc
RAS
.