HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 58

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5 On-Demand Data Transfer Mode (DDT Mode)................................................................ 603
14.6 Configuration of the DMAC (SH7750R).......................................................................... 634
14.7 Register Descriptions (SH7750R)..................................................................................... 640
14.8 Operation (SH7750R) ....................................................................................................... 647
14.9 Usage Notes ...................................................................................................................... 652
Section 15 Serial Communication Interface (SCI)
15.1 Overview........................................................................................................................... 655
15.2 Register Descriptions ........................................................................................................ 659
Rev.7.00 Oct. 10, 2008 Page lvi of lxxxiv
REJ09B0366-0700
14.4.1 Examples of Transfer between External Memory and an External Device with
14.5.1 Operation ............................................................................................................. 603
14.5.2 Pins in DDT Mode............................................................................................... 605
14.5.3 Transfer Request Acceptance on Each Channel .................................................. 608
14.5.4 Notes on Use of DDT Module ............................................................................. 631
14.6.1 Block Diagram of the DMAC.............................................................................. 634
14.6.2 Pin Configuration (SH7750R) ............................................................................. 636
14.6.3 Register Configuration (SH7750R) ..................................................................... 637
14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7) .......................................... 640
14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7).................................. 640
14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7)......................... 641
14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7)................................... 641
14.7.5 DMA Operation Register (DMAOR) .................................................................. 645
14.8.1 Channel Specification for a Normal DMA Transfer............................................ 647
14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 647
14.8.3 Transfer Channel Notification in DDT Mode ...................................................... 648
14.8.4 Clearing Request Queues by DTR Format........................................................... 649
14.8.5 Interrupt-Request Codes ...................................................................................... 649
15.1.1 Features................................................................................................................ 655
15.1.2 Block Diagram..................................................................................................... 657
15.1.3 Pin Configuration................................................................................................. 658
15.1.4 Register Configuration......................................................................................... 658
15.2.1 Receive Shift Register (SCRSR1)........................................................................ 659
15.2.2 Receive Data Register (SCRDR1) ....................................................................... 660
15.2.3 Transmit Shift Register (SCTSR1) ...................................................................... 660
15.2.4 Transmit Data Register (SCTDR1)...................................................................... 661
15.2.5 Serial Mode Register (SCSMR1)......................................................................... 661
15.2.6 Serial Control Register (SCSCR1)....................................................................... 664
15.2.7 Serial Status Register (SCSSR1).......................................................................... 667
15.2.8 Serial Port Register (SCSPTR1) .......................................................................... 671
DACK .................................................................................................................. 602
.................................................... 655