HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 217
HD6417750RF200DV
Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF200DV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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4.4.3
Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address.
This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is
performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled
as two areas by means of effective address bit [25], providing efficient use of the cache.
4.5
To enable the IC and OC to be managed by software, their contents can be read and written by a
P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access
is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should
be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4
area in physical memory space. Only data accesses can be used on both the IC address array and
data array and the OC address array and data array, and accesses are always longword-size.
Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should
be specified; their read value is undefined.
4.5.1
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The entry to be accessed is specified in the address field, and the
write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry
is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit
[3] association bit (A bit) specifies whether or not association is performed when writing to the IC
address array. As only longword access is used, 0 should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
IC Index Mode
Memory-Mapped Cache Configuration (SH7750, SH7750S)
IC Address Array
Rev.7.00 Oct. 10, 2008 Page 131 of 1074
REJ09B0366-0700
Section 4 Caches
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