HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 521

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
When area 3 is accessed, the CS3 signal is asserted.
When SRAM interface is set, the RD signal, which can be used as OE, and write control signals
WE0 to WE7, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (RDY).
The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3
register.
When synchronous DRAM interface is set, the RAS and CAS signals, RD/WR signal, and byte
control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. When
DRAM interface is set, the RAS signal, CAS0 to CAS7 signals, and RD/WR signal are asserted,
and address multiplexing is performed. RAS, CAS, and data timing control, and address
multiplexing control, can be set using the MCR register.
Area 4: For area 4, external address bits A28 to A26 are 100.
SRAM, MPX, and byte control SRAM can be set to this area.
A bus width of 8, 16, 32, or 64 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2
register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits
A4SZ1 and A4SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus
width of 16, 32, or 64 bits. For details, see Memory Bus Width in section 13.1.5, Overview of
Areas.
When area 4 is accessed, the CS4 signal is asserted, and the RD signal, which can be used as OE,
and write control signals WE0 to WE7, are also asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (RDY).
The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3
register.
Rev.7.00 Oct. 10, 2008 Page 435 of 1074
REJ09B0366-0700