HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 142

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 Programming Model
Rev.7.00 Oct. 10, 2008 Page 56 of 1074
REJ09B0366-0700
Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and
31
(a) Register configuration
2. Banked registers
3. Banked registers
4. Banked registers
in user mode
indexed GBR indirect addressing mode.
Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is set to 1.
R0 _ BANK0
R1 _ BANK0
R2 _ BANK0
R3 _ BANK0
R4 _ BANK0
R5 _ BANK0
R6 _ BANK0
R7 _ BANK0
MACH
Figure 2.2 CPU Register Configuration in Each Processor Mode
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1 *2
*2
*2
*2
*2
*2
*2
*2
0
31
(b) Register configuration in
privileged mode (RB = 1)
R0 _ BANK1
R0 _ BANK0
R7 _ BANK0
R1 _ BANK1
R2 _ BANK1
R3 _ BANK1
R4 _ BANK1
R5 _ BANK1
R6 _ BANK1
R7 _ BANK1
R1 _ BANK0
R2 _ BANK0
R3 _ BANK0
R4 _ BANK0
R5 _ BANK0
R6 _ BANK0
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
*1 *3
*1 *4
*4
*3
*3
*3
*3
*3
*3
*3
*4
*4
*4
*4
*4
*4
0
31
(c) Register configuration in
privileged mode (RB = 0)
R0 _ BANK0
R0 _ BANK1
R1 _ BANK0
R2 _ BANK0
R3 _ BANK0
R4 _ BANK0
R5 _ BANK0
R6 _ BANK0
R7 _ BANK0
R1 _ BANK1
R2 _ BANK1
R3 _ BANK1
R4 _ BANK1
R5 _ BANK1
R6 _ BANK1
R7 _ BANK1
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
R8
R9
SR
PC
*1 *4
*1 *3
*4
*4
*4
*4
*4
*4
*4
*3
*3
*3
*3
*3
*3
*3
0