DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 619

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8
22.8.1
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR_1 (WDT_1) PSS bit = 1, CPU operation shifts to sub-sleep mode.
In sub-sleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, TMR_2
to TMR_4 * , WDT_0, WDT_1, and LCD are also stopped. The contents of the CPU’s internal
registers, the data in internal RAM, and the statuses of the internal peripheral modules (excluding
the A/D converter) and I/O ports are retained.
Note: * Supported only by the H8S/2268 Group.
22.8.2
Sub-sleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin, or
IRQ0, IRQ1, IRQ3, IRQ4, IRQ5 * , or WKP0 to WKP7), or signals at the RES or STBY pins.
• Exiting Sub-Sleep Mode by Interrupts
• Exiting Sub-Sleep Mode by RES
• Exiting Sub-Sleep Mode by STBY Pin
Note: * Supported only by the H8S/2268 Group.
When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts.
In the case of IRQ0, IRQ1, IRQ3, IRQ4, IRQ5 * , and WKP0 to WKP7 interrupts, sub-sleep
mode is not cancelled if the corresponding enable bit/pin function switching bit has been
cleared to 0, and, in the case of interrupts from the internal peripheral modules, the interrupt
enable register has been set to disable the reception of that interrupt, or is masked by the CPU.
For exiting sub-sleep mode by the RES pins, see section 22.4.2, Clearing Software Standby
Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Sub-Sleep Mode
Transition to Sub-Sleep Mode
Exiting Sub-Sleep Mode
Rev. 5.00 Sep. 01, 2009 Page 567 of 656
Section 22 Power-Down Modes
REJ09B0071-0500