DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 429

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

and 1 is output from the TxD pin. To send a break during serial transmission, first set PDR to 1
and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized
regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from
the TxD pin.
13.9.4
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
13.9.5
• When an external clock source is used as the serial clock, the transmit clock should not be
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI
• The flags are automatically cleared to 0 by DTC during the data transfer only when the DISEL
input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 13.36)
reception data full interrupt (RXI).
bit in DTC is 0 with the transfer counter other than 0. When the DISEL bit in the
corresponding DTC is 1, or both the DISEL bit and the transfer counter are 0, give the CPU an
Instruction to clear flags. Note that, particularly during transmission, the TDRE flag that is not
cleared by the CPU causes incorrect transmission.
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Restrictions on Use of DTC (H8S/2268 Group Only)
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
Figure 13.36 Example of Clocked Synchronous Transmission by DTC
t
LSB
D0
D1
D2
Section 13 Serial Communication Interface (SCI)
D3
Rev. 5.00 Sep. 01, 2009 Page 377 of 656
D4
D5
D6
D7
REJ09B0071-0500