DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 469

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal.
The slave device compares its own address with the slave address in the first frame following the
establishment of the start condition issued by the master device. If the addresses match, the slave
device operates as the slave device designated by the master device.
Figure 14.14 is a flowchart showing an example of slave receive mode operation.
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
Figure 14.13 Example of Master Receive Mode Stop Condition Generation Timing
Slave Receive Operation
Data 2
Bit 0
8
[6] IRIC clearance
[4] IRTR = 0
[3]
Section 14 I
Data 1
A
[8]
1 clock cycle wait time
[4] IRTR = 1
9
[7] ACKB set to 1
[3]
Bit 7
2
[9] TRS set to 1
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
1
(MLS = ACKB = 0, WAIT = 1)
Data 2
[10] ICDR read (data 2)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
[11] IRIC clearance
3
4
Data 3
5
6
Rev. 5.00 Sep. 01, 2009 Page 417 of 656
7
[14] IRIC clearance
8
[15] WAIT cleared to 0
[13] IRTR = 0
[12]
IRIC clearance
A
[13] IRTR = 1
[12]
9
[16] ICDR read (data 3)
Data 3
REJ09B0071-0500
[17] Stop condition
issued
Stop condition
generated