DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 115

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.4
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. Interrupts are accepted even within the trace exception handling
routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling
is not carried out after execution of the RTE instruction.
Table 4.3
Legend:
1:
0:
—: Retains value prior to execution
4.5
Interrupts are controlled by the interrupt controller. The interrupt controller of the H8S/2268
Group has two interrupt control modes and can assign interrupts other than NMI to eight
priority/mask levels to enable multiplexed interrupt control. For details, refer to section 5,
Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
2. The interrupt mask bit is updated and the T bit * is cleared to 0.
register (EXR) * are saved to the stack.
Set to 1
Cleared to 0
Interrupt Control Mode
Traces (Supported Only by the H8S/2268 Group)
Interrupts
Status of CCR and EXR after Trace Exception Handling
0
2
1
I
Trace exception handling cannot be used.
CCR
UI
—
Rev. 5.00 Sep. 01, 2009 Page 63 of 656
Section 4 Exception Handling
I2 to I0
—
REJ09B0071-0500
EXR
T
0