DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 475

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations
in slave transmit mode are described below.
1. Initialize slave receive mode and wait for slave address reception.
2. When the slave address matches in the first frame following detection of the start condition,
3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the TDRE internal flag is
4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
5. To continue transmission, write the next data to be transmitted into ICDR. The TDRE internal
Transmit operations can be performed continuously by repeating steps [4] and [5].
6. Clear the IRIC flag to 0.
When making initial settings for slave receive mode, set the ACKE bit in ICCR to 1. This is
necessary in order to enable reception of the acknowledge bit after entering slave transmit
mode.
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
TDRE internal flag is set to 1. The slave device drives SCL low from the fall of the transmit
clock until ICDR data is written, to disable the master device to output the next transfer clock.
cleared to 0. The written data is transferred to ICDRS, and the TDRE internal and IRIC flags
are set to 1 again. The slave device sequentially sends the data written into ICDRS in
accordance with the clock output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR
writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt
processing from being inserted. If the time for transmission of one frame of data has passed
before the IRIC clearing, the end of transmission cannot be determined.
This acknowledge signal is stored in the ACKB bit in ICSR if the ACKE bit in has been set to
1, so the ACKB bit can be used to determine whether the transfer operation was performed
successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1
at the rise of the 9th transmit clock pulse. When the TDRE internal flag is 0, the data written
into ICDR is transferred to ICDRS, transmission starts, and the TDRE internal and IRIC flags
are set to 1 again. If the TDRE internal flag has been set to 1, this slave device drives SCL low
from the fall of the transmit clock until data is written to ICDR.
flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing
from the ICDR register writing to the IRIC flag clearing should be performed continuously.
Prevent any other interrupt processing from being inserted.
Section 14 I
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Rev. 5.00 Sep. 01, 2009 Page 423 of 656
REJ09B0071-0500