DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 363

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit
7
6
Bit Name
GM
BLK
Initial
Value
0
0
R/W
R/W
R/W
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM mode.
In GSM mode, the timing of the TEND setting is
advanced by 11.0 etu (Elementary Time Unit: the time for
transfer of one bit), and clock output control mode
addition is performed. For details, refer to section 13.7.8,
Clock Output Control.
0: Normal smart card interface mode operation (initial
1: GSM mode operation in smart card interface mode
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode, refer to
section 13.7.3, Block Transfer Mode.
0: Normal smart card interface mode operation (initial
1: Operation in block transfer mode
value)
• The TEND flag is generated 12.5 etu (11.5 etu in the
• Clock output on/off control only
• The TEND flag is generated 11.0 etu after the
• In addition to clock output on/off control, high/low
value)
• Error signal transmission, detection, and automatic
• The TXI interrupt is generated by the TEND flag.
• The TEND flag is set 12.5 etu (11.0 etu in the GSM
• Error signal transmission, detection, and automatic
• The TXI interrupt is generated by the TDRE flag.
• The TEND flag is set 11.5 etu (11.0 etu in the GSM
block transfer mode) after the beginning of the start
bit.
beginning of the start bit.
fixed control is supported (set using SCR).
data retransmission are performed.
mode) after transmission starts.
data retransmission are not performed.
mode) after transmission starts.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 311 of 656
REJ09B0071-0500