DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 164

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
7.1.2
Addresses H'FFFDAC to H'FFFFBF in the on-chip peripheral modules are accessed in two states.
The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being
accessed. For details, refer to section 24, List of Registers. Figure 7.2 shows access timing for the
on-chip peripheral modules (H'FFFDAC to H'FFFFBF).
7.1.3
Addresses H'FFFC30 to H'FFFCA3 on the on-chip peripheral modules and registers are accessed
in four states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O
register being accessed. For details, refer to section 24, List of Registers. Figure 7.3 shows access
timing for the on-chip peripheral modules (H'FFFC30 to H'FFFCA3).
The on-chip module of which address is between H'FFFC30 to H'FFFCA3 includes LCD,
DTMF * , TMR4 * , ports H to L and ports M * and N * . The registers are WKP register and module
stop control register D.
Note: * Supported only by the H8S/2268 Group.
Rev. 5.00 Sep. 01, 2009 Page 112 of 656
REJ09B0071-0500
Figure 7.2 On-Chip Peripheral Module Access Cycle (H'FFFDAC to H'FFFFBF)
On-Chip Peripheral Module Access Timing (H'FFFDAC to H'FFFFBF)
On-Chip Peripheral Module Access Timing (H'FFFC30 to H'FFFCA3)
Internal address bus
Read
access
Write
access
φ
Internal read signal
Internal data bus
Internal write signal
Internal data bus
T1
Bus cycle
Address
Write data
Read data
T2