DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 31

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3 Operation........................................................................................................................... 296
12.4 Interrupt Sources............................................................................................................... 299
12.5 Usage Notes ...................................................................................................................... 299
Section 13 Serial Communication Interface (SCI) ............................................303
13.1 Features ............................................................................................................................. 303
13.2 Input/Output Pins .............................................................................................................. 307
13.3 Register Descriptions ........................................................................................................ 307
13.4 Operation in Asynchronous Mode .................................................................................... 338
13.5 Multiprocessor Communication Function......................................................................... 349
13.6 Operation in Clocked Synchronous Mode ........................................................................ 355
12.3.1 Watchdog Timer Mode ........................................................................................ 296
12.3.2 Interval Timer Mode ............................................................................................ 297
12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 298
12.3.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF) ............................. 298
12.5.1 Notes on Register Access..................................................................................... 299
12.5.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 301
12.5.3 Changing Value of CKS2 to CKS0...................................................................... 301
12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 301
12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 302
12.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 302
12.5.7 Notes on Initializing TCNT by Using the TME Bit............................................. 302
13.3.1 Receive Shift Register (RSR) .............................................................................. 308
13.3.2 Receive Data Register (RDR) .............................................................................. 308
13.3.3 Transmit Data Register (TDR)............................................................................. 308
13.3.4 Transmit Shift Register (TSR) ............................................................................. 309
13.3.5 Serial Mode Register (SMR)................................................................................ 309
13.3.6 Serial Control Register (SCR).............................................................................. 313
13.3.7 Serial Status Register (SSR) ................................................................................ 318
13.3.8 Smart Card Mode Register (SCMR) .................................................................... 325
13.3.9 Bit Rate Register (BRR) ...................................................................................... 326
13.3.10 Serial Expansion Mode Register (SEMR_0) ....................................................... 334
13.4.1 Data Transfer Format........................................................................................... 338
13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous
13.4.3 Clock.................................................................................................................... 341
13.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 342
13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................ 343
13.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 345
13.5.1 Multiprocessor Serial Data Transmission ............................................................ 351
13.5.2 Multiprocessor Serial Data Reception ................................................................. 352
Mode .................................................................................................................... 340
Rev. 5.00 Sep. 01, 2009 Page xxix of l
REJ09B0071-0500