DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 248

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Sep. 01, 2009 Page 196 of 656
REJ09B0071-0500
7, 6
Bit
5
4
3
2
1
0
Bit Name
BFB
BFA
MD3
MD2
MD1
MD0
Initial
value
All 1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be modified.
H8S/2268 Group:
Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register,
TGRD input capture/output compare is not generated.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
H8S/2264 Group:
Reserved
These bits are always read as 0 and cannot be modified.
H8S/2268 Group:
Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1:TGRA and TGRC used together for buffer operation
H8S/2264 Group:
Reserved
These bits are always read as 0 and cannot be modified.
Modes 0 to 3
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, it should always be
written with 0. See table 10.8 for details.

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