DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 457

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.8
DDCSWR controls the I
clear.
Legend:
X: Don’t care
Notes: 1. Only 0 can be written to these bits.
Bit
7 to 4
3
2
1
0
2. Supported only by the H8S/2268 Group.
Bit Name
⎯
CLR3
CLR2
CLR1
CLR0
DDC Switch Register (DDCSWR)
Section 14 I
Initial
Value
All 0
1
1
1
1
2
C bus interface format automatic switching function and internal latch
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
R/W
R/(W) *
W
W
W
W
1
Description
Reserved
The write value should always be 0.
I
When bits CLR3 to CLR0 are set, a clear signal is
generated for the I
and the internal state is initialized. The write data for
these bits is not retained. To perform I
CLR3 to CLR0 must be written to simultaneously using
an MOV instruction. Do not use a bit manipulation
instruction such as BCLR.
00XX: Setting prohibited
0100: Setting prohibited
0101: IIC_0 Internal latch cleared
0110: IIC_1 *
0111: IIC_0, IIC_1 *
1XXX: Invalid setting
2
C Bus Interface Clear 3 to 0:
2
Internal Iatch cleared
Rev. 5.00 Sep. 01, 2009 Page 405 of 656
2
C bus interface internal latch circuit,
2
Internal Iatch cleared
2
C clearance, bits
REJ09B0071-0500