DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 461

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 14.7 Flowchart for Master Transmit Mode (Example)
Section 14 I
No
No
No
No
No
Write transmit data to ICDR
Write transmit data to ICDR
Read BBSY flag in ICCR
Read ACKB bit in ICSR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
and TRS = 1 (ICCR)
and SCP = 0 (ICCR)
Transmit complete?
Write ACKE = 0 (ICCR)
Write BBSY = 0 and
Transmit mode?
Write BBSY = 1
(Clear ACKB = 0)
SCP = 0 (ICCR)
Initial settings
Set MST = 1
(ACKB = 1?)
ACKB = 0?
BBSY = 0?
IRIC = 1?
IRIC = 1?
IRIC = 1?
Yes
Start
End
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1] Initial settings.
[2] Determine status of SCL and SDA lines.
[3] Set to master transmit mode.
[4] Generate start condition.
[5] Wait for start condition to be met.
[6] Set 1st byte (slave address + R/W) transmit data.
[7] Wait for end of 1 byte transmission.
[8] Judge acknowledge signal from specified.
[9] Set transmit data for 2nd byte onward.
[10] Wait for end of 1 byte transmission.
[11] Judge end of transmission.
[12] Generate stop condition.
Master receive mode
(Perform ICDR write and IRIC flag clear
operations continuously.)
slave device.
(Perform ICDR write and IRIC flag clear
operations continuously.)
Rev. 5.00 Sep. 01, 2009 Page 409 of 656
REJ09B0071-0500

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