DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 483

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 14.8 Permissible SCL Rise Time (t
6. The I
IICX
0
1
and 300 ns. The I
shown in table 14.7. However, because of the rise and fall times, the I
specifications may not be satisfied at the maximum transfer rate. Table 14.9 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times. The values in the above table will vary depending on the settings of the
IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to
achieve the maximum transfer rate; therefore, whether or not the I
specifications are met must be determined in accordance with the actual setting conditions.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
BUFO
SCLLO
t
Indication
7.5 t
17.5 t
cyc
fails to meet the I
2
in high-speed mode and t
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Section 14 I
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
2
I
Specification
(Max.)
1000 ns
300 ns
1000 ns
300 ns
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
2
C Bus
STASO
in standard mode fail to satisfy the I
sr
) Values
φ =
5 MHz
1000 ns
300 ns
1000 ns
300 ns
Sr
/t
Sf
. Possible solutions that should be
Rev. 5.00 Sep. 01, 2009 Page 431 of 656
φ =
8 MHz
937 ns
300 ns
1000 ns
300 ns
Time Indication
φ =
10 MHz
750 ns
300 ns
1000 ns
300 ns
2
C bus interface
2
C bus.
2
C bus interface
2
C bus interface
φ =
16 MHz
468 ns
300 ns
1000 ns
300 ns
REJ09B0071-0500
Scyc
and t
φ =
20 MHz
375 ns
300 ns
875 ns
300 ns
cyc
2
C
, as