DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 244

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
Common Registers
• Timer start register (TSTR)
• Timer synchro register (TSYR)
Note: * Supported only by the H8S/2268 Group.
10.3.1
The TCR registers control the TCNT operation for each channel. The H8S/2268 Group TPU has a
total of three TCR registers and the H8S/2264 Group TPU has a total of two TCR registers, one
for each channel (channels 0 to 2, or 1 and 2). TCR register settings should be conducted only
when TCNT operation is stopped.
Rev. 5.00 Sep. 01, 2009 Page 192 of 656
REJ09B0071-0500
7
6
5
Bit
4
3
2
1
0
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
Initial
value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source. See
tables 10.3 and 10.4 for details.
Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock period
is halved (e.g. φ/4 both edges = φ/2 rising edge). Internal
clock edge selection is valid when the input clock is φ/4 or
slower. If the input clock is φ/1, this setting is ignored and
count at falling edge of φ is selected. In the H8S/2268
Group, if phase counting mode is used on channels 1 and
2, this setting is ignored and the phase counting mode
setting has priority.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Legend: X: Don’t care
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables10.5 to10.7 for details.