DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 42

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
(H8S/2268 Group Only)......................................................................................... 248
Figure 10.46 Contention between TCNT Write and Clear Operations........................................ 249
Figure 10.47 Contention between TCNT Write and Increment Operations ................................ 249
Figure 10.48 Contention between TGR Write and Compare Match ........................................... 250
Figure 10.49 Contention between Buffer Register Write and Compare Match........................... 251
Figure 10.50 Contention between TGR Read and Input Capture ................................................ 252
Figure 10.51 Contention between TGR Write and Input Capture ............................................... 253
Figure 10.52 Contention between Buffer Register Write and Input Capture............................... 254
Figure 10.53 Contention between Overflow and Counter Clearing ............................................ 255
Figure 10.54 Contention between TCNT Write and Overflow.................................................... 256
Section 11 8-Bit Timers
Figure 11.1 Block Diagram of 8-Bit Timer Module.................................................................. 258
Figure 11.2 Example of Pulse Output........................................................................................ 268
Figure 11.3 Count Timing for Internal Clock Input................................................................... 269
Figure 11.4 Count Timing for External Clock Input ................................................................. 269
Figure 11.5 Timing of CMF Setting .......................................................................................... 270
Figure 11.6 Timing of Timer Output ......................................................................................... 270
Figure 11.7 Timing of Compare-Match Clear ........................................................................... 271
Figure 11.8 Timing of Clearing by External Reset Input .......................................................... 271
Figure 11.9 Timing of OVF Setting........................................................................................... 272
Figure 11.10 Contention between TCNT Write and Clear .......................................................... 275
Figure 11.11 Contention between TCNT Write and Increment................................................... 276
Figure 11.12 Contention between TCOR Write and Compare-Match ........................................ 277
Figure 11.13 Block Diagram of 8-Bit Reload Timer ................................................................... 281
Figure 11.14 Operation in Interval Timer Mode ......................................................................... 284
Figure 11.15 Operation in Automatic Reload Timer Mode......................................................... 285
Figure 11.16 Channel Relationship of Cascaded Connection...................................................... 286
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of WDT_0 ..................................................................................... 290
Figure 12.2 Block Diagram of WDT_1 ..................................................................................... 290
Figure 12.3 Watchdog Timer Mode Operation.......................................................................... 297
Figure 12.4 Interval Timer Mode Operation.............................................................................. 297
Figure 12.5 Timing of OVF Setting........................................................................................... 298
Figure 12.6 Timing of WOVF Setting....................................................................................... 298
Figure 12.7 Writing to TCNT, TCSR (WDT_0) ....................................................................... 299
Figure 12.8 Writing to RSTCSR ............................................................................................... 300
Figure 12.9 Contention between TCNT Write and Increment................................................... 301
Rev. 5.00 Sep. 01, 2009 Page xl of l
REJ09B0071-0500