DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 371

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
5
4
Bit Name
ORER
FER
Initial
Value
0
0
R/W
R/(W) *
R/(W) *
1
1
Description
Overrun Error
Indicates that an overrun error occurred during reception,
causing abnormal termination.
[Setting condition]
When the next serial reception is completed while RDRF
= 1
The receive data prior to the overrun error is retained in
RDR, and the data received subsequently is lost. Also,
subsequent serial reception cannot be continued while
the ORER flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued either.
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
The ORER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
Framing Error
Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
[Setting condition]
When the stop bit is 0
In 2 stop bit mode, only the first stop bit is checked for a
value to 1; the second stop bit is not checked. If a framing
error occurs, the receive data is transferred to RDR but
the RDRF flag is not set. Also, subsequent serial
reception cannot be continued while the FER flag is set to
1. In clocked synchronous mode, serial transmission
cannot be continued, either.
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
The FER flag is not affected and retains its previous state
when the RE bit in SCR is cleared to 0.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 319 of 656
REJ09B0071-0500