DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 578

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 ROM
Rev. 5.00 Sep. 01, 2009 Page 526 of 656
REJ09B0071-0500
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written
Reprogram Data Computation Table
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of 30 μs or 200 μs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths.
Original Data
Note 6: Write Pulse Width
Note: * Use a 10 μs write pulse for additional programming.
to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case,
H'FF data must be written to the extra addresses.
the data stored in the program data area and the verify data). Bits for which the reprogram data is 0
are programmed in the next reprogramming loop. Therefore, even bits for which programming has been
completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
When writing of additional-programming data is executed, a 10 μs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Number of Writes n
(D)
0
0
1
1
Write pulse application subroutine
1000
998
999
Clear PSU1 bit in FLMCR1
10
11
12
13
1
2
3
4
5
6
7
8
9
Reprogram data storage
Additional-programming
Set PSU1 bit in FLMCR1
Sub-Routine Write Pulse
Clear P1 bit in FLMCR1
Program data storage
Verify Data
Set P1 bit in FLMCR1
Wait t
data storage area
area (128 bytes)
area (128 bytes)
Wait (t
(V)
Wait (t
(128 bytes)
Wait (t
0
1
0
1
WDT enable
Disable WDT
sp10 or 30 or 200
RAM
End Sub
spsu
cpsu
cp
Reprogram Data
) 5 μs
(tsp30/tsp200) μs
) 50 μs
) 5 μs
Write Time
(X)
1
0
1
1
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
*
*
*
*
*
*
Figure 20.10 Program/Program-Verify Flowchart
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Start of programming
End of programming
*
5
Comments
Increment address
Additional-Programming Data Computation Table
Reprogram Data
Successively write 128-byte data from additional-
(X')
programming data area in RAM to flash memory
0
0
1
1
Apply Write Pulse (Additional programming)
No
Transfer reprogram data to reprogram data area
Additional-programming data computation
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Apply Write pulse t
Verify Data
Clear SWE1 bit in FLMCR1
Set SWE1 bit in FLMCR1
Reprogram data computation
data verification completed?
Clear PV1 bit in FLMCR1
Set PV1 bit in FLMCR1
Start of programming
(V)
0
1
0
1
Wait (t
End of programming
Wait (t
t
Wait (t
spvr
Read verify data
Wait (t
Yes
Yes
Write data =
verify data?
Yes
128-byte
START
m = 0 ?
m = 0
= Wait 2 μs
6
cswe
6
n = 1
sswe
Programming Data (Y)
≥
spv
≥
cpv
n ?
n?
Yes
Yes
) 100 μs
) 4 μs
Sub-Routine-Call
Sub-Routine-Call
) μs
) 1 μs
sp
Additional-
30 or 200
0
1
1
1
No
No
No
*
*
*
No
See Note 6 for pulse width
4
1
2
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
*
*
*
3
4
4
*
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
1
Clear SWE1 bit in FLMCR1
Wait (t
Programming failure
Comments
n ≥ 1000?
cswe
Yes
) 100 μs
No
n ← n + 1
Reprogram