DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 30

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.6 Operation with Cascaded Connection ............................................................................... 273
11.7 Interrupt Sources............................................................................................................... 274
11.8 Usage Notes ...................................................................................................................... 275
11.9 8-Bit Reload Timer (TMR_4) (H8S/2268 Group Only) ................................................... 280
11.10 Register Descriptions ........................................................................................................ 282
11.11 Operation........................................................................................................................... 284
11.12 Usage Notes ...................................................................................................................... 287
Section 12 Watchdog Timer (WDT) .................................................................289
12.1 Features ............................................................................................................................. 289
12.2 Register Descriptions ........................................................................................................ 291
Rev. 5.00 Sep. 01, 2009 Page xxviii of l
REJ09B0071-0500
11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs.............. 270
11.5.3 Timing of Timer Output When a Compare-Match Occurs .................................. 270
11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs .................... 271
11.5.5 TCNT External Reset Timing .............................................................................. 271
11.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 272
11.6.1 16-Bit Count Mode .............................................................................................. 273
11.6.2 Compare-Match Count Mode .............................................................................. 273
11.7.1 Interrupt Sources and DTC Activation ................................................................ 274
11.7.2 A/D Converter Activation.................................................................................... 274
11.8.1 Setting Module Stop Mode .................................................................................. 275
11.8.2 Contention between TCNT Write and Clear........................................................ 275
11.8.3 Contention between TCNT Write and Increment ................................................ 276
11.8.4 Contention between TCOR Write and Compare-Match ...................................... 277
11.8.5 Contention between Compare-Matches A and B................................................. 277
11.8.6 Switching of Internal Clocks and TCNT Operation............................................. 278
11.8.7 Contention between Interrupts and Module Stop Mode ...................................... 279
11.9.1 Features................................................................................................................ 280
11.9.2 Input/Output Pins ................................................................................................. 281
11.10.1 Timer Control Registers 4 to 7 (TCR_4 to TCR_7)............................................. 282
11.10.2 Timer Counters 4 to 7 (TCNT4 to TCNT7)......................................................... 283
11.10.3 Time Reload Registers 4 to 7 (TLR_4 to TLR_7) ............................................... 283
11.11.1 Interval Timer Operation ..................................................................................... 284
11.11.2 Automatic Reload Timer Operation..................................................................... 285
11.11.3 Cascaded Connection........................................................................................... 285
11.12.1 Conflict between Write to TLR and Count Up/Automatic Reload ...................... 287
11.12.2 Switchover of Internal Clock and TCNT Operation ............................................ 287
11.12.3 Interrupt during Module Stop .............................................................................. 287
12.2.1 Timer Counter (TCNT)........................................................................................ 291
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 291
12.2.3 Reset Control/Status Register (RSTCSR) (Only WDT_0) .................................. 295