DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 498

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 A/D Converter
15.3
The A/D converter has the following registers. For details on the module stop control register,
refer to section 22.1.2, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD).
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
15.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 15.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits width. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. Therefore,
when reading the ADDR, read only the upper byte, or read in word unit.
Table 15.2 Analog Input Channels and Corresponding ADDR Registers
Rev. 5.00 Sep. 01, 2009 Page 446 of 656
REJ09B0071-0500
Group 0
(CH2 = 0)
AN0
AN1
AN2
AN3
A/D Data Registers A to D (ADDRA to ADDRD)
Register Descriptions
CH3 = 0
Group 1
(CH2 = 1)
AN4
AN5
AN6
AN7
Analog Input Channel
⎯
(CH2 = 0)
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
CH3 = 1
⎯
(CH2 = 1)
Setting
prohibited
Setting
prohibited
AN8
AN9
A/D Data Register to be
Stored Results of A/D
Conversion
ADDRA
ADDRB
ADDRC
ADDRD