DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 45

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 14.22 Flowchart and Timing of Start Condition Instruction Issuance for
Figure 14.23 Timing of Stop Condition Issuance........................................................................ 436
Figure 14.24 IRIC Flag Clearance in WAIT = 1 Status .............................................................. 436
Figure 14.25 ICDR Read and ICCR Access Timing in Slave Transmit Mode............................ 437
Figure 14.26 TRS Bit Setting Timing in Slave Mode ................................................................. 438
Figure 14.27 Diagram of Erroneous Operation when Arbitration Is Lost ................................... 440
Figure 14.28 Timing of IRIC Flag Clearing during Wait Operation ........................................... 441
Section 15 A/D Converter
Figure 15.1 Block Diagram of A/D Converter .......................................................................... 444
Figure 15.2 Access to ADDR (When Reading H'AA40)........................................................... 450
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ........... 452
Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Figure 15.5 A/D Conversion Timing......................................................................................... 454
Figure 15.6 External Trigger Input Timing ............................................................................... 456
Figure 15.7 A/D Conversion Accuracy Definitions (1)............................................................. 458
Figure 15.8 A/D Conversion Accuracy Definitions (2)............................................................. 458
Figure 15.9 Example of Analog Input Circuit ........................................................................... 459
Figure 15.10 Example of Analog Input Protection Circuit.......................................................... 461
Figure 15.11 Analog Input Pin Equivalent Circuit ...................................................................... 461
Section 16 D/A Converter
Figure 16.1 Block Diagram of D/A Converter .......................................................................... 463
Figure 16.2 D/A Converter Operation Example ........................................................................ 467
Section 17 LCD Controller/Driver.....................................................................469
Figure 17.1 Block Diagram of LCD Controller/Driver ............................................................. 470
Figure 17.2 A Waveform 1/2 Duty 1/2 Vias.............................................................................. 480
Figure 17.3 Handling of LCD Drive Power Supply when Using 1/2 Duty ............................... 482
Figure 17.4 LCD RAM Map (1/4 Duty).................................................................................... 484
Figure 17.5 LCD RAM Map (1/3 Duty).................................................................................... 484
Figure 17.6 LCD RAM Map (1/2 Duty).................................................................................... 485
Figure 17.7 LCD RAM Map (Static Mode) .............................................................................. 485
Figure 17.8 Output Waveforms for Each Duty Cycle (A Waveform) ....................................... 486
Figure 17.9 Output Waveforms for Each Duty Cycle (B Waveform) ....................................... 487
Figure 17.10 Connection when Triple Step-Up Voltage Circuit Used (Supported Only by
Figure 17.11 Example of Low-Power-Consumption LCD Drive Operation ............................... 491
Figure 17.12 Connection of External Split-Resistance................................................................ 492
Retransmission ....................................................................................................... 435
Selected) ................................................................................................................. 453
the H8S/2268 Group) ............................................................................................. 489
Rev. 5.00 Sep. 01, 2009 Page xliii of l
REJ09B0071-0500

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